1. Field of the Invention
The present invention relates to design for test and debug, specifically, response determinism using synchronization techniques.
2. Description of the Related Art
As the technology for manufacturing integrated circuits advances, more logic functions are included in a single integrated circuit device or a system on a chip (SoC). Modem integrated circuit (IC) devices include large numbers of gates on a single semiconductor chip, with these gates interconnected so as to perform multiple and complex functions. The fabrication of an IC incorporating such Very Large Scale Integration (VLSI) must be error free, as a single manufacturing defect may prevent the IC from performing all of the functions that an IC or SoC is designed to perform. Such demands require verification of the design of the IC or SoC and also various types of electrical testing after the IC or SoC is manufactured.
Typically, automatic test equipment (ATE) facilitates testing of the chip, or device under test (DUT), via a plurality of test and control signals. Point to point (pTp) systems that utilize interconnects such as, PCI-Express or CSI, require determinism in order to accurately determine the timing of a response with respect to a clock signal, such as a master or reference clock.
The ATE injects test vectors in to the DUT and obtains responses in a specific pre-calculated time slots ensuring validation and high efficiency. In components that utilize point to point links, tester injects and checks vectors through the links. For example, the vector may flow through several stages such as physical layer and uncore Logic before reaching the processor core. Determinism in the device is required to achieve practical tester efficiency. A repeatable, deterministic alignment of events in all the blocks of the component produces a predictable test response.
Current implementations, such as PCI-Express, are not predictable to a clock cycle due to the transmission delay from the interconnect links with respect to a clock signal and achieve DUT response determinism by searching for a known pattern in a response from the DUT. The searching operations, also known as hunting, are time critical and can take several milliseconds. These searching operations are inefficient, increase the testing time and therefore the overall hardware cost.